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1 for more information www.linear.com/ltc4235 typical a pplica t ion fea t ures descrip t ion dual 12 v ideal diode - or a nd s ingle hot swap controller with current monitor the lt c ? 4235 offers ideal diode-or and hot swap tm functions for two 12 v power rails by controlling external n-channel mosfets. mosfets acting as ideal diodes replace two high power schottky diodes and the associ - ated heat sinks, saving power and board area. a hot swap control mosfet allows a board to be safely inserted and removed from a live backplane by limiting inrush current. the supply output is also protected against short-circuit faults with a foldback current limit and circuit breaker. the ltc4235 regulates the forward voltage drop across the mosfets to ensure smooth current transfer from one supply to the other without oscillation. the ideal diodes turn on quickly to reduce the load voltage droop during supply switchover. if the input supply fails or is shorted, a fast turn-off minimizes reverse-current transients. a current sense amplifier translates the voltage across the sense resistor to a ground referenced signal. the ltc4235 allows turn-on/off control, and reports fault and power good status for the supply. a pplica t ions n ideal diode-or and inrush current control for redundant supplies n low loss replacement for power schottky diodes n enables safe board insertion into a live backplane n 9v to 14v operation n current monitor output n controls n-channel mosfets n limits peak fault current in 1s n adjustable current limit with foldback n adjustable current limit fault delay n 0.5s ideal diode turn-on and turn-off time n smooth switchover without oscillation n fault and power good outputs n ltc4235-1: latch off after fault n ltc4235-2: automatic retry after fault n 20-pin 4mm x 5mm qfn package n redundant power supplies n high availability systems and servers n telecom and network infrastructure l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 7920013, 8022679. ideal diode-or with hot swap application 12v 12v cpo1 gnd on pwrgd imon fault 13.7k c load 12v 7a 2k intv cc d2off in1 dgate1 dgate2 ltc4235 4235 ta01a sir158dp sir158dp 0.003 hgate out sense + sense ? cpo2 0.1f in2 + 0.1f sir158dp en 0.1f 0.1f ftmr reg 0.1f adc smooth supply switchover 200ms/div in1 1v/div in2 1v/div i in1 2a/div i in2 2a/div 4235 ta01b in1 in2 ltc 4235 4235f
2 for more information www.linear.com/ltc4235 a bsolu t e maxi m u m r a t ings supply voltages in 1, in 2 .................................................. C 0.3 v to 24 v int v cc ..................................................... C0. 3 v to 7v reg ........................... sense + C 5v to sense + + 0.3 v input voltages on , d 2off, en ...................................... C 0.3 v to 24 v ft mr ..................................... C 0.3 v to intv cc + 0.3 v sense + , sense C ................................... C0. 3 v to 24 v output voltages imo n ....................................................... C 0.3 v to 7v fa u lt , pwrgd ...................................... C 0.3 v to 24 v cpo 1, cpo 2 ( note 3) ............................. C 0.3 v to 35 v dg ate 1, dgate 2 ( note 3) ..................... C 0.3 v to 35 v hg ate ( note 4) ..................................... C 0.3 v to 35 v out ....................................................... C0. 3 v to 24 v average currents fa u lt , pwrgd .................................................... 5 ma int v cc ............................................................... 10 ma op erating ambient temperature range ltc 42 35 c ................................................ 0 c to 70 c ltc 42 35 i ............................................. C4 0 c to 85 c storage temperature range .................. C 65 c to 150 c 20 19 18 17 7 8 top view 21 ufd package 20-lead (4mm 5mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 sense ? sense + in1 intv cc gnd in2 pwrgd fault on d2off reg imon dgate1 cpo1 hgate out dgate2 cpo2 ftmr en t jmax = 125c, ja = 43c/w (note 5) exposed pad ( pin 21) pcb gnd connection op tional p in c on f igura t ion o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc4235cufd-1#pbf ltc4235cufd-1#trpbf 42351 20-lead (4mm x 5mm) plastic qfn 0c to 70c ltc4235cufd-2#pbf ltc4235cufd-2#trpbf 42352 20-lead (4mm x 5mm) plastic qfn 0c to 70c ltc4235iufd-1#pbf ltc4235iufd-1#trpbf 42351 20-lead (4mm x 5mm) plastic qfn C40c to 85c ltc4235iufd-2#pbf ltc4235iufd-2#trpbf 42352 20-lead (4mm x 5mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. (notes 1, 2) ltc 4235 4235f
3 for more information www.linear.com/ltc4235 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. symbol parameter conditions min typ max units supplies v in input supply range l 9 14 v i in input supply current l 2.7 4 ma v intvcc internal regulator voltage i = 0, C500a l 4.5 5 5.5 v v intvcc(uvl) internal v cc undervoltage lockout intv cc rising l 2.1 2.2 2.3 v ?v intvcc(hyst) internal v cc undervoltage lockout hysteresis l 30 60 90 mv ideal diode control ? v fwd (reg) forward regulation voltage (v inn C v sense +) l 2 15 28 mv ? v dgate external n-channel gate drive (v dgaten C v inn ) ? v fwd = 0.15v; i = 0, C1a l 10 12 14 v i cpo(up) cpon pull-up current cpo = in = 12v l C50 C90 C120 a i dgate(fpu) dgaten fast pull-up current ? v fwd = 0.2v, ? v dgate = 0v, cpo = 17v C1.5 a i dgate(fpd) dgaten fast pull-down current ? v fwd = C0.2v, ? v dgate = 5v 1.5 a i dgate2(dn) dgate2 off pull-down current d2off = 2v, ? v dgate2 = 2.5v l 50 100 200 a t on(dgate) dgaten turn-on delay ? v fwd = 0.2v , c dgate = 10nf l 0.25 0.5 s t off(dgate) dgaten turn-off delay ? v fwd = C0.2v, c dgate = 10nf l 0.2 0.5 s t plh(dgate2) d2off low to dgate2 high l 50 100 s hot swap control ? v sense(th) current limit sense voltage threshold (v sense + C v sense C) out = 11v out = 0v l l 22.5 5.8 25 8.3 27.5 10.8 mv mv v sense + (uvl) sense + undervoltage lockout sense + rising l 1.8 1.9 2 v ?v sense + (hyst) sense + undervoltage lockout hysteresis l 10 50 90 mv i sense + sense + pin current sense + = 12v l 0.3 0.8 1.3 ma i sense C sense C pin current sense C = 12v l 10 40 100 a ? v hgate external n-channel gate drive (v hgate ?C?v out ) i = 0, C1a l 10 12 14 v ? v hgate(h) gate high threshold (v hgate C v out ) l 3.6 4.2 4.8 v i hgate(up) external n-channel gate pull-up current gate drive on, hgate = 0v l C7 C10 C13 a i hgate(dn) external n-channel gate pull-down current gate drive off, out = 12v, hgate = out + 5v l 1 2 4 ma i hgate(fpd) external n-channel gate fast pull-down current fast turn-off, out = 12v, hgate = out + 5v l 100 200 350 ma v out(pgth) out power good threshold out rising l 10.2 10.5 10.8 v ? v out(pghyst) out power good hysteresis l 110 170 240 mv t phl(sense) sense voltage (sense + C sense C ) high to hgate low ? v sense = 200mv, c hgate = 10nf l 0.5 1 s t off(hgate) on low to hgate low en high to hgate low sense + low to hgate low sense + uvlo l l l 10 20 10 20 40 20 s s s t d(hgate) on high, en low to hgate turn-on delay l 50 100 150 ms t p(hgate) on to hgate propagation delay on = step 0.8v to 2v l 10 20 s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, unless otherwise noted. ltc 4235 4235f
4 for more information www.linear.com/ltc4235 symbol parameter conditions min typ max units inputs v d2off(h,th) d2off pin high threshold d2off rising l 1.21 1.235 1.26 v v d2off(l,th) d2off pin low threshold d2off falling l 1.19 1.215 1.24 v ? v d2off(hyst) d2off pin hysteresis l 10 20 30 mv v on(th) on pin threshold voltage on rising l 1.21 1.235 1.26 v v on(reset) on pin fault reset threshold voltage on falling l 0.57 0.6 0.63 v ? v on(hyst) on pin hysteresis l 40 80 120 mv i in(leak) input leakage current (on, d2off) v = 5v l 0 1 a v en(th) en pin threshold voltage en rising l 1.185 1.235 1.284 v ? v en(hyst) en pin hysteresis l 60 110 200 mv i en(up) en pull-up current en = 1v l C7 C10 C13 a v ftmr(h) ftmr pin high threshold l 1.198 1.235 1.272 v v ftmr(l) ftmr pin low threshold l 0.15 0.2 0.25 v i ftmr(up) ftmr pull-up current ftmr = 1v, in fault mode l C80 C100 C120 a i ftmr(dn) ftmr pull-down current ftmr = 2v, no faults l 1.3 2 2.7 a d retry auto-retry duty cycle l 0.07 0.15 0.23 % t rst(on) on low to fault high l 20 40 s outputs i out out pin current out = 11v, in = 12v, on = 2v out = 13v, in = 12v, on = 2v l l 30 100 2.5 170 4 a ma v ol output low voltage ( fault , pwrgd ) i = 1ma i = 3ma l l 0.15 0.4 0.4 1.2 v v v oh output high voltage ( fault , pwrgd ) i = C1a l intv cc C 1 int v cc C 0.5 v i oh input leakage current ( fault, pwrgd ) v = 18v l 0 1 a i pu output pull-up current ( fault, pwrgd ) v = 1.5v l C7 C10 C13 a current monitor ? v reg floating regulator voltage (v sense + C v reg ) i reg = 1a l 3.6 4.1 4.6 v ? v sense(fs) input sense voltage full scale (v sense + C v sense C) sense + = 12v l 25 mv v imon(os) imon input offset voltage ? v sense = 0v l 150 v g imon imon voltage gain ? v sense = 20mv and 5mv l 99 100 101 v/v v imon(max) imon maximum output voltage ? v sense = 70mv l 3.5 5.5 v v imon(min) imon minimum output voltage ? v sense = 200v l 40 mv r imon(out) imon output resistance ? v sense = 200v l 15 20 27 k e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in = 12v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of the device pins are negative. all voltages are referenced to gnd unless other wise specified. note 3: an internal clamp limits the dgate and cpo pins to a minimum of 10v above and a diode below in. driving these pins to voltages beyond the clamp may damage the device. note 4: an internal clamp limits the hgate pin to a minimum of 10v above and a diode below out. driving this pin to voltages beyond the clamp may damage the device. note 5: thermal resistance is specified when the exposed pad is soldered to a 3" x 5", four layer, fr4 board. ltc 4235 4235f
5 for more information www.linear.com/ltc4235 typical p er f or m ance c harac t eris t ics hot swap gate voltage vs current hot swap gate voltage vs in voltage cpo voltage vs current diode gate voltage vs current diode gate voltage vs in voltage fault , pwrgd output low voltage vs current in supply current vs voltage sense + current vs voltage out current vs voltage t a = 25c, v in = 12v, unless otherwise noted. v in (v) 0 i in (ma) 3.5 3 2 1 2.5 1.5 0.5 0 6 12 4235 g01 18 3 15 9 v sense + = v in ? 0.5v v out = 12v v out = 0v v sense + (v) 0 i sense + (ma) 1.4 1.2 0.8 0.4 1 0.6 0.2 0 6 12 4235 g02 18 3 15 9 v out (v) 0 i out (ma) 3.5 3 2 1 2.5 1.5 0.5 ?0.5 0 6 12 4235 g03 18 3 15 9 v in = 12v, v sense + = 11.5v i hgate (a) 0 ?v hgate (v) 14 12 10 8 6 4 2 0 ?4 ?8 4235 g04 ?12 ?2 ?10 ?6 v out = v in v in = 12v v in (v) 0 ?v hgate (v) 14 12 10 8 6 4 6 12 4235 g05 18 3 15 9 v out = v in i cpo (a) 0 v cpo ? v in (v) 12 0 10 8 6 4 2 ?2 ?40 ?120 ?80 4235 g06 ?140 ?20 ?100 ?60 i dgate (a) 0 ?v dgate (v) 12 0 10 8 6 4 2 ?2 ?40 ?120 ?80 4235 g07 ?140 ?20 ?100 ?60 v sense + = v in ? 0.15v v in = 12v v in (v) 0 ?v dgate (v) 14 12 10 8 6 4 6 12 4235 g08 18 3 15 9 v sense + = v in ? 0.15v current (ma) 0 output low voltage (v) 0.6 0.5 0.3 0.1 0.4 0.2 0 2 4 4235 g09 5 1 3 ltc 4235 4235f
6 for more information www.linear.com/ltc4235 typical p er f or m ance c harac t eris t ics imon voltage vs sense voltage imon voltage gain vs temperature imon propagation delay vs sense voltage ideal diode start-up waveform on in power-up hgate start-up waveform on on toggling high current limit threshold foldback current limit delay vs sense voltage current sense amplifier input offset voltage vs temperature t a = 25c, v in = 12v, unless otherwise noted. v out (v) 0 current limit sense voltage v sense + ? v sense ? (mv) 30 25 20 15 5 10 0 4 8 4235 g10 12 2 10 6 sense voltage (v sense + ? v sense ?) (mv) 0 current limit delay (s) 100 10 1 0.1 80 120 4235 g11 200 40 160 c hgate = 10nf 10ms/div in 10v/div sense + 10v/div 10v/div 4235 g16 cpo dgate 20ms/div on 5v/div hgate 10v/div out 10v/div pwrgd 10v/div 4235 g17 temperature (c) ?50 input offset voltage (v) 40 30 20 10 35 25 15 5 0 0 50 4235 g12 100 ?25 75 25 sense voltage (v sense + ? v sense ?) (mv) 0 imon voltage (v) 5 3 2 1 4 0 20 40 4235 g13 50 10 30 temperature (c) ?50 imon voltage gain (v/v) 101 100 100.5 99.5 99 0 50 4235 g14 100 ?25 75 25 sense voltage (v sense + ? v sense ?) (mv) 0 imon propagation delay (s) 120 60 40 20 80 100 0 2 4 4235 g15 5 1 3 ltc 4235 4235f
7 for more information www.linear.com/ltc4235 p in func t ions cpo1, cpo2: charge pump output. connect a capacitor from cpo1 or cpo2 to the corresponding in1 or in2 pin. the value of this capacitor is approximately 10 x the gate capacitance (c iss ) of the external mosfet for ideal diode control. the charge stored on this capacitor is used to pull up the ideal diode mosfet gate during a fast turn-on. leave this pin open if fast ideal diode turn- on is not needed. dgate1, dgate2: ideal diode mosfet gate drive out - put. connect this pin to the gate of an external n-channel mosfet for ideal diode control. an internal clamp limits the gate voltage to 12v above and a diode voltage below in. during fast turn- on, a 1.5 a pull- up charges dgate from cpo. during fast turn-off, a 1.5 a pull-down discharges dgate to in. d2off: control input. a rising edge above 1.235 v turns off the external ideal diode mosfet in the in2 supply path and a falling edge below 1.215 v allows the mosfet to be turned on. connect this pin to an external resistive divider from in1 to make in1 the higher priority input supply when in1 and in2 are equal . en : enable input. ground this pin to enable hot swap control. if this pin is pulled high, the hot swap mosfet is not allowed to turn on. a 10 a current source pulls this pin up to a diode below intv cc . upon en going low when on is high, there is a start-up delay of 100 ms for debounce, after which the fault is cleared. fault : overcurrent fault status output. output that pulls low when the fault timer expires during an overcurrent fault. otherwise it is pulled high by a 10 a current source to a diode below intv cc . it may be pulled above intv cc using an external pull-up. leave open if unused. ftmr : fault timer capacitor terminal. connect a capacitor between this pin and ground to set a 12 ms/f duration for current limit before the external hot swap mosfet is turned off. the duration of the off time is 8 s/f, resulting in a 0.15% duty cycle. gnd: device ground. hgate: hot swap mosfet gate drive output. connect this pin to the gate of the external n-channel mosfet for hot swap control. an internal 10 a current source charges the mosfet gate. an internal clamp limits the gate volt- age to 12 v above and a diode voltage below out. during an undervoltage generated turn-off, a 2 ma pull-down discharges hgate to ground. during an output short or intv cc undervoltage lockout, a fast 200 ma pull-down discharges hgate to out. in1, in2: positive supply input and ideal diode mosfet gate drive return. connect this pin to the power input side of the external ideal diode mosfet. the 5 v intv cc supply is generated from in1, in2 and out via an internal diode-or. the voltage sensed at this pin is used to control dgate. the gate fast pull-down current returns through this pin when dgate is discharged. intv cc : internal 5 v supply decoupling output. this pin must have a 0.1 f or larger capacitor to gnd. an external load of less than 500a can be connected at this pin. an undervoltage lockout threshold of 2.2 v will turn off both mosfets. imon: current sense monitoring output. this pin voltage is proportional to the sense voltage across the current sense resistor with a voltage gain of 100. an internal 20k resistor is connected from this pin to ground. on: on control input. a rising edge above 1.235v turns on the external hot swap mosfet and a falling edge below 1.155v turns it off. connect this pin to an external resistive divider from sense + to monitor the supply undervoltage condition. pulling the on pin below 0.6 v resets the fault latch after an overcurrent fault. tie to intv cc if unused. out: hot swap mosfet gate drive return. connect this pin to the output side of the external mosfet. the gate fast pull-down current returns through this pin when hgate is discharged. an internal resistive divider connected be - tween this pin and gnd is used for current limit foldback and power good monitor for 12 v operation. if the out voltage falls below 10.33 v, the pwrgd pin pulls high to indicate the power is bad. if the voltage falls below 7.65v, the output current limit is reduced. ltc 4235 4235f
8 for more information www.linear.com/ltc4235 p in func t ions pwrgd : power status output. output that pulls low when the out pin rises above 10.5 v and the mosfet gate drive between hgate and out exceeds 4.2 v. otherwise it is pulled high by a 10 a current source to a diode below intv cc . it may be pulled above intv cc using an external pull-up. leave open if unused. reg: internal regulated supply for current sense ampli - fier. a 0.1 f or larger capacitor should be tied from reg to sense + . this pin is not designed to drive external circuits. sense + : positive current sense input. connect this pin to the diode-or output of the external ideal diode mosfets and input of the current sense resistor. the voltage sensed at this pin is used for monitoring the current limit and also to control dgate for forward voltage regulation and reverse turn-off. this pin has an undervoltage lockout threshold of 1.9 v that will turn off the hot swap mosfet. sense C : negative current sense input. connect this pin to the output of the current sense resistor. the current limit circuit controls hgate to limit the voltage between sense + and sense C to 25 mv or less depending on the voltage at the out pin. ltc 4235 4235f
9 for more information www.linear.com/ltc4235 b lock diagra m ? + + ? + ? + ? cl + ? cm ? + ? + ? + + ? 1.235v en logic en 4235 bd exposed pad gate driver cpo1 0.9v foldback 150k 20k intv cc 10a intv cc intv cc 10a fault pwrgd cpo2 imon in1 sense ? in2 reg sense + pg1 pg2 10.5v hgate 4.2v uvlo1 uvlo2 1.9v 2.2v sense + out intv cc ? + ? + 0.6v rst fault reset 1.235v on hgate on ? + ? + 0.2v tm2 1.235v ftmr tm1 10a intv cc 100a 2a gnd dgate2 off + ? 1.235v doff d2off on 5v ldo charge pump 2 f = 2mhz 100a 100a charge pump 1 f = 2mhz 10a dgate1 dgate2 15mv 15mv gd2 gd1 12v 12v 12v out out 20k 200 4.1v hgate ltc 4235 4235f
10 for more information www.linear.com/ltc4235 o pera t ion the ltc4235 functions as an input supply diode-or with inrush current limiting and overcurrent protection by controlling the external n-channel mosfets (m d1 , m d2 and m h ) on a supply path. this allows boards to be safely inserted and removed in systems with a backplane powered by redundant supplies. the ltc4235 has a single hot swap controller and two separate ideal diode controllers, each providing independent control for the two input supplies. when the ltc4235 is first powered up, the gates of the external mosfets are held low, keeping them off. as the dgate2 pull - up can be disabled by the d2 off pin, dgate 2 will pull high only when the d2off pin is pulled low. the gate drive amplifier ( gd1, gd2) monitors the voltage be - tween the in and sense + pins and drives the respective dgate pin. the amplifier quickly pulls up the dgate pin, turning on the mosfet for ideal diode control, when it senses a large forward voltage drop. with the ideal diode mosfets acting as input supply diode-or, the sense + pin voltage rises to the highest of the supplies at the in1 and in2 pins. an external capacitor connected at the cpo pin provides the charge needed to quickly turn on the ideal diode mosfet. an internal charge pump charges up this capacitor at device power-up. the dgate pin sources current from the cpo pin and sinks current into the in and gnd pins. pulling the on pin high and en pin low initiates a 100ms debounce timing cycle. after this timing cycle, a 10 a cur - rent sour ce from the charge pump ramps up the hgate pin. when the hot swap mosfet turns on, the inrush current is limited at a level set by an external sense resistor (r s ) connected between the sense + and sense C pins. an active current limit amplifier ( cl) servos the gate of the mosfet to 25 mv or less across the current sense resistor depending on the voltage at the out pin. inrush current can be further reduced, if desired, by adding a capacitor from hgate to gnd. when out voltage rises above 10.5 v and the mosfets gate drive ( hgate to out voltage) exceeds 4.2v, the pwrgd pin pulls low. the high side current sense amplifier ( cm) provides ac - curate monitoring of current through the current sense resistor. the sense voltage is amplified by 100 times and level shifted from the positive rail to a ground-referred output at the imon pin. the output signal is analog and may be used as is or measured with an adc. when the ideal diode mosfet is turned on, the gate drive amplifier controls dgate to servo the forward voltage drop (v in C v sense +) across the mosfet to 15 mv. if the load current causes more than 15 mv of voltage drop, the gate voltage rises to enhance the mosfet. for large output currents, the mosfets gate is driven fully on and the voltage drop is equal to i load ?r ds(on) of the mosfet. in the case of an input supply short-circuit when the mosfets are conducting, a large reverse current starts flowing from the load towards the input. the gate drive amplifier detects this failure condition and turns off the ideal diode mosfet by pulling down the dgate pin. in the case where an overcurrent fault occurs on the sup - ply output , the current is limited with foldback. after a delay set by 100 a charging the ftmr pin capacitor, the fault timer expires and pulls the hgate pin low, turning off the hot swap mosfet. the f ault pin is also latched low. at this point, the dgate pin continues to pull high and keeps the ideal diode mosfet on. internal clamps limit both the dgate to in and cpo to in voltages to 12 v. the same clamp also limits the dgate and cpo pins to a diode voltage below the in pin. another internal clamp limits the hgate to out voltage to 12v and also clamps the hgate pin to a diode voltage below the out pin. power to the ltc4235 is supplied from either the in or out pins, through an internal diode-or circuit to a low dropout regulator ( ldo). that ldo generates a 5 v supply at the intv cc pin and powers the ltc4235s internal low voltage circuitry. ltc 4235 4235f
11 for more information www.linear.com/ltc4235 high availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. power oring diodes are com - monly used to connect these supplies at the point of load at the expense of power loss due to significant diode forward voltage drop. the ltc4235 minimizes this power loss by using external n-channel mosfets as the pass elements, allowing for a low voltage drop from the supply to the load when the mosfets are turned on. when an input source voltage drops below the output common supply voltage, the appropriate mosfet is turned off, thereby matching the function and performance of an ideal diode. by adding a current sense resistor and a hot swap mosfet after the parallel-connected ideal diode mosfets, the ltc4235 enhances the ideal diode performance with inrush current limiting and overcurrent protection ( see figure?1). this allows the board to be safely inserted and removed from a live backplane without damaging the connector. internal v cc supply the ltc4235 operates with an input supply from 9 v to 14v. the power supply to the device is internally regulated at 5 v by a low dropout regulator ( ldo) with an output at the int v cc pin. an internal diode-or circuit selects the a pplica t ions i n f or m a t ion highest of the supplies at the in and out pins to power the device through the ldo . the diode - or scheme permits the devices power to be kept alive by the out voltage when the in supplies have collapsed or shut off. an undervoltage lockout circuit prevents all of the mosfets from turning on until the intv cc voltage exceeds 2.2 v. a 0.1f capacitor is recommended between the intv cc and gnd pins, close to the device for bypassing. no external supply should be connected at the intv cc pin so as not to affect the ldos operation. a small external load of less than 500a can be connected at the intv cc pin. turn-on sequence the board power supply at the out pin is controlled with external n-channel mosfets (m d1 , m d2 and m h ) in figure?1. the ideal diode mosfets connected in parallel on the supply side function as a diode-or, while m h on the load side acts as a hot swap mosfet controlling the power supplied to the output load. the sense resistor r s monitors the load current for overcurrent detection. the hga te capacitor c hg controls the gate slew rate to limit the inrush current. resistor r hg with c hg compensates the current control loop, while r h prevents high frequency oscillations in the hot swap mosfet. figure?1. card resident diode-or with hot swap application backplane connector v in1 12v v in2 12v card connector cpo1 gnd on fault pwrgd imon adc c l 680f 12v 7a r1 2k intv cc z2 smaj15a d2off in1 dgate1 dgate2 ltc4235 4235 f01 m d2 sir158dp m h sir158dp r s 0.003 hgate out sense + sense ? cpo2 c3 0.1f c4 0.1f in2 + r2 13.7k r3 100k r4 100k r h 10 r hg 1k c hg 10nf reg c2 0.1f c1 0.1f m d1 sir158dp en c ft 0.1f c5 0.1f z1 smaj15a ftmr ltc 4235 4235f
12 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion during a normal power-up, the ideal diode mosfets turn on first. as soon as the internally generated supply, intv cc , rises above its 2.2 v undervoltage lockout threshold, the internal charge pump is allowed to charge up the cpo pins. because the ideal diode mosfets are connected in parallel as a diode-or, the sense + pin voltage approaches the highest of the supplies at the in1 and in2 pins. the mosfet associated with the lower input supply voltage will be turned off by the corresponding gate drive amplifier. before the hot swap mosfet can be turned on, en must remain low and on must remain high for a 100ms debounce timing cycle to ensure that any contact bounces during the insertion have ceased. at the end of the debounce cycle, the internal fault latch is cleared. the hot swap mosfet is then allowed to turn on by charging up hgate with a 10a current source from the charge pump. the voltage at the hgate pin rises with a slope equal to 10 a/c hg and the supply inrush current flowing into the load capacitor c l is limited to: i inrush = c l c hg ? 10a the out voltage follows the hgate voltage when the hot swap mosfet turns on. if the voltage across the current sense resistor r s becomes too high based on the out pin voltage, the inrush current will be limited by the internal current limiting circuitry. once the mosfet gate overdrive exceeds 4.2 v and the out pin voltage is above 10.5v, the pwrgd pin pulls low to indicate that the power is good. once out reaches the input supply voltage, hgate continues to ramp up. an internal 12 v clamp limits the hgate voltage above out. when the ideal diode mosfet is turned on, the gate drive amplifier controls the gate of the mosfet to servo the forward voltage drop across the mosfet to 15mv. if the load current causes more than 15 mv of drop, the mosfet gate is driven fully on and the voltage drop is equal to i load ?r ds(on) . turn-off sequence the external mosfets can be turned off by a variety of conditions. a normal turn-off for the hot swap mosfet is initiated by pulling the on pin below its 1.155 v threshold (80mv on pin hysteresis), or pulling the en pin above its 1.235 v threshold . additionally, an overcurrent fault that exceeds the fault timer period also turns off the hot swap mosfet. normally, the ltc4235 turns off the mosfet by pulling the hgate pin to ground with a 2 ma current sink. all of the mosfets turn off when intv cc falls below its undervoltage lockout threshold (2.2 v). the dgate pin is pulled down with a 100 a current to one diode voltage below the in pin, while the hgate pin is pulled down to the out pin by a 200 ma current. when d2off is pulled high above 1.235 v, the ideal diode mosfet in the in2 power path is turned off with dgate2 pulled low by a 100a current. the gate drive amplifier controls the ideal diode mosfet to prevent reverse current when the input supply falls below sense + . if the input supply collapses quickly, the gate drive amplifier turns off the ideal diode mosfet with a fast pull-down circuit. if the input supply falls at a more modest rate, the gate drive amplifier controls the mosfet to maintain sense + at 15mv below in. board presence detect with en if on is high when the en pin goes low, indicating a board presence, the ltc4235 initiates a debounce timing cycle for contact debounce. upon board insertion, any bounces on the en pin restart the timing cycle. when the debounce timing cycle is done, the internal fault latch is cleared. if the en pin remains low at the end of the timing cycle, hgate is charged up with a 10 a current source to turn on the hot swap mosfet. if the en pin goes high, indicating a board removal, the hgate pin is pulled low with a 2 ma current sink after a 20s delay, turning off the hot swap mosfet without clearing any latched fault. ltc 4235 4235f
13 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion overcurrent fault the ltc4235 features an adjustable current limit with foldback that protects the external mosfet against short circuits or excessive load current. the voltage across the external sense resistor r s is monitored by an active cur- rent limit amplifier. the amplifier controls the gate of the hot swap mosfet to reduce the load current as a func- tion of the output voltage sensed by the out pin during active current limit. a graph in the typical performance characteristics shows the current limit sense voltage versus out voltage. an overcurrent fault occurs when the output has been in current limit for longer than the fault timer period configured at the ftmr pin. current limiting begins when the sense voltage between the sense + and sense C pins reaches 8.3mv to 25 mv depending on the out pin voltage. the gate of the hot swap mosfet is brought under control by the current limit amplifier and the output current is regu - lated to limit the sense voltage to less than 25 mv. at this point, the fault timer starts with a 100 a current charging the ftmr pin capacitor. if the ftmr pin voltage exceeds its 1.235 v threshold, the external mosfet turns off with hga te pulled to ground by 2ma and fault pulls low. after the hot swap mosfet turns off, the ftmr pin ca - pacitor is discharged with a 2 a pull-down current until its threshold reaches 0.2 v. this is followed by a cool-off period of 14 timing cycles as described in the ftmr pin functions. figure? 2 shows an overcurrent fault on the 12v output. 200s/div out 10v/div hgate 10v/div i load 20a/div 4235 f02 figure?2. overcurrent fault on 12v output 5s/div out 10v/div hgate 10v/div i load 20a/div 4235 f03 figure?3. severe short-circuit on 12v output in the event of a severe short-circuit fault on the 12 v output as shown in figure?3, the output current can surge to tens of amperes. the ltc4235 responds within 1 s to bring the current under control by pulling the hgate to out voltage down to zero volts. almost immediately, the gate of the hot swap mosfet recovers rapidly due to the charge stored in the r hg and c hg network and current is actively limited until the fault timer expires. due to parasitic supply lead inductance, an input supply without any bypass capaci - tor may collapse during the high current surge and then spike upwards when the current is interrupted. figure?10 shows the input supply transient suppressors comprising of z1, r snub1 , c snub1 and z2, r snub2 , c snub2 for the two supplies if there is no input capacitance. ftmr pin functions an external capacitor c ft connected from the ftmr pin to gnd serves as fault timing when the supply output is in active current limit. when the voltage across the sense resistor exceeds the foldback current limit threshold (from 25mv to 8.3 mv), ftmr pulls up with 100 a. otherwise, it pulls down with 2 a. the fault timer expires when the 1.235v ftmr threshold is exceeded, causing the fault pin to pull low. for a given fault timer period, the equation for setting the external capacitor c ft value is: c ft = t ft ? 0.083 [f/ms] after the fault timer expires, the ftmr pin capacitor pulls down with 2 a from the 1.235 v ftmr threshold until it reaches 0.2v . then, it completes 14 cooling cycles consist - ing of the ftmr pin capacitor charging to 1.235 v with a ltc 4235 4235f
14 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion 100a current and discharging to 0.2 v with a 2 a current. at that point, the hgate pin voltage is allowed to start up if the fault has been cleared as described in the resetting fault section. when the latched fault is cleared during the cool-off period, the fault pin pulls high. the total cool-off time for the mosfet after an overcurrent fault is: t cool = c ft ? 8 [s/f] after the cool-off period, the hgate pin is only allowed to pull up if the fault has been cleared for the latchoff part. for the auto-retry part, the latched fault is cleared automatically following the cool-off period and the hgate pin voltage is allowed to restart. resetting fault (ltc4235-1) for the latchoff part, an overcurrent fault is latched after the fault timer expires and the fault pin is asserted low. only the hot swap mosfet is turned off and the ideal diode mosfets are not affected. to reset a latched fault and restart the output, pull the on pin below 0.6 v for more than 100 s and then high above 1.235 v. the fault latch resets and the fault pin de-asserts on the falling edge of the on pin. when on goes high again and the cool-off cycle has completed, a debounce timing cycle is initiated before the hgate pin voltage restarts. toggling the en pin high and then low again also resets a fault, but the fault pin pulls high at the end of the debounce cycle before the hgate pin volt - age starts up. bringing all the supplies below the intv cc undervoltage lockout threshold (2.2 v) shuts off all the mosfets and resets the fault latch. a debounce cycle is initiated before a normal start-up when any of the supplies is restored above the intv cc uvlo threshold. auto-retry after a fault (ltc4235-2) for the auto-retry part, the latched fault is reset automati - cally at the end of the cool-off period as described in the f tmr pin functions section. at the end of the cool-off period, the fault latch is cleared and fault pulls high. the hgate pin voltage is allowed to start up and turn on the hot swap mosfet. if the output short persists, the supply powers up into a short with active current limiting until the fault timer expires and fault again pulls low. a new cool -off cycle begins with ftmr ramping down with a 2 a current. the whole process repeats itself until the output short is removed. since t ft and t cool are a function of ftmr capacitance c ft , the auto-retry cycle is equal to 0.15%, irrespective of c ft . figure? 4 shows an auto-retry sequence after an over - current fault. 100ms/div ftmr 2v/div fault 10v/div hgate 20v/div out 10v/div 4235 f04 figure?4. auto-retry sequence after a fault monitor undervoltage fault the on pin functions as a turn-on control and an input supply monitor. a resistive divider connected between the supply diode-or output (sense + ) and gnd at the on pin monitors the supply for undervoltage condition. the undervoltage threshold is set by proper selection of the resistors at the on rising threshold voltage (1.235 v). for figure? 1, if r 1 = 2 k, r2 = 13.7 k, the input supply undervoltage threshold is set to 9.7v. an undervoltage fault occurs if the diode-or output sup - ply falls below its undervoltage threshold. if the on pin voltage falls below 1.155 v but remains above 0.6 v, the hot swap mosfet is turned off by a 2 ma pull-down from hgate to ground. the hot swap mosfet turns back on instantly without the debounce cycle when the diode-or output supply rises above its undervoltage threshold. however, if the on pin voltage drops below 0.6 v, it turns off the hot swap mosfet and clears the fault latch. the hot swap mosfet turns back on only after a debounce cycle when the diode-or output supply is restored above its undervoltage threshold. ltc 4235 4235f
15 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion during the undervoltage fault condition, fault will not be pulled low but pwrgd will be pulled high as hgate is pulled low. the ideal diode function controlled by the ideal diode mosfet is not affected by the undervoltage (uv) fault condition. power good monitor internal circuitry monitors the mosfet gate overdrive between the hgate and out pins. also, an internal resis - tive divider that connects to out is used to determine a power good condition. the power good comparator drives high when the out pin rises above 10.5 v, and drives low when out falls below 10.33 v. the power good status for the input supply is reported via an open-drain output, pwrgd . it is normally pulled high by an external pull-up resistor or the internal 10a pull-up. the pwrgd pin pulls low when the out power good comparator is high and the hgate drive exceeds 4.2 v. the pwrgd pin goes high when the hgate is turned off by the on or en pins, or when the out power good comparator drives low, or when intv cc enters undervoltage lockout. current sense monitor the current through the external sense resistor is monitored by a ltc4235s current sense amplifier at the sense + and sense C pins ( see figure?5). the amplifier uses auto- zeroing circuitry to achieve an offset below 150 v over temperature, sense voltage and input supply voltage. the frequency of the auto-zero clock is 10 khz. an internal resistor r in is connected between the amplifiers negative input terminal and sense + pin. the sense amplifier loop forces the negative input terminal to have the same potential as sense C and that develops a potential across r in to be the same as the sense voltage v sense . a corresponding current, v sense /r in , will flow through r in . the high impedance inputs of the sense amplifier will not conduct this input current, allowing it to flow through an internal mosfet to a resistor r out connected between the imon and gnd pins. the imon output voltage is equal to (r out / r in )??? v sense . the resistor ratio r out /r in defines the voltage gain of the sense amplifier and is set to 100 with r in = 200 and r out = 20 k. full scale input sense voltage to the sense amplifier is 25 mv, corresponding to an output of 2.5 v. the output clamps at 3.5 v if the allowable input sense voltage range is exceeded. imon output filtering a capacitor connected in parallel with r out will give a low pass response. this will reduce unwanted noise at the output, and may also be useful as a charge reservoir to keep the output steady while driving a switching circuit such as an adc ( see figure? 5). this output capacitor c out in parallel with r out will create a pole in the output response at: f c = 1 2 ? ? r out ? c out 0.1f 0.1f 10f 5v imon v out i load v cc r in 200 0.1f 12v v sense r out 20k 2-wire i 2 c interface ltc4235 4235 f05 hgate load sense + ref + ref ? sense ? gnd gnd reg scl sda ltc2451 in v out = CCCCC ? v sense = 100 ? v sense r out r in figure?5. high side current monitor with ltc2451 adc ltc 4235 4235f
16 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion reg pin bypassing the ltc4235 has an internally regulated supply near sense + for internal bias of the current sense amplifier. it is not intended for use as a supply or bias pin for external circuitry. a 0.1 f capacitor should be connected between the reg and sense + pins. this capacitor should be located very near to the device and close to the reg pin for the best performance. reg and imon start-up the start-up current of the current sense amplifier when the ltc4235 is powered on consists of two parts: the first is the current necessary to charge the reg bypass capacitor, which is nominally 0.1 f. since the reg voltage charges to approximately 4.1 v below the sense + voltage, this can require a significant amount of start-up current. the second source is the output current that flows into r out , which upon start-up may temporarily drive the imon output high for less than 2 ms. this is a temporary condition which will cease when the sense amplifier settles into normal closed-loop operation. cpo and dgate start-up the cpo and dgate pin voltages are initially pulled up to a diode below the in pin when first powered up. cpo starts ramping up 7 s after intv cc clears its undervolt- age lockout level. another 40 s later, dgate also starts ramping up with cpo. the cpo ramp rate is determined by the cpo pull-up current into the combined cpo and dgate pin capacitances. an internal clamp limits the cpo pin voltage to 12 v above the in pin, while the final dgate pin voltage is determined by the gate drive amplifier. an internal 12 v clamp limits the dgate pin voltage above in. cpo capacitor selection the recommended value of the capacitor between the cpo and in pins is approximately 10 the input capacitance c iss of the ideal diode mosfet. a larger capacitor takes a correspondingly longer time to charge up by the internal charge pump. a smaller capacitor suffers more voltage drop during a fast gate turn-on event as it shares charge with the mosfet gate capacitance. mosfet selection the ltc4235 drives n-channel mosfets to conduct the load current. the important features of the mosfets are on - resistance r ds ( on ) , the maximum drain - source voltage bv dss and the threshold voltage. the gate drive for the ideal diode and hot swap mosfet is guaranteed to be greater than 10 v and is limited to 14v. an external zener diode can be used to clamp the potential from the mosfets gate to source if the rated breakdown voltage is less than 14v. the maximum allowable drain- source voltage bv dss must be higher than the supply voltage including supply transients as the full supply voltage can appear across the mosfet. if an input or output is connected to ground, the full supply voltage will appear across the mosfet. the r ds(on) should be small enough to conduct the maximum load current, and also stay within the mosfets power rating. supply transient protection when the capacitances at the input and output are very small, rapid changes in current during input or output short-circuit events can cause transients that exceed the 24v absolute maximum ratings of the in and out pins. to minimize such spikes, use wider traces or heavier trace plating to reduce the power trace inductance. also, bypass locally with a 10 f electrolytic and 0.1 f ceramic, or alternatively clamp the input with a transient voltage suppressor ( z1, z2). a 100, 0.1 f snubber damps the response and eliminates ringing (see figure?10). design example as a design example for selecting components, consider a 12v system with a 7 a maximum load current for the two supplies (see figure?1). first, select the appropriate value of the current sense resistor r s for the 12 v supply. calculate the sense resistor value based on the maximum load current i load(max) and ltc 4235 4235f
17 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion the lower limit for the current limit sense voltage threshold ? v sense(th)(min) . r s = v sense(th)(min) i load(max) = 22.5mv 7a = 3.2m choose a 3m sense resistor with a 1% tolerance. next, calculate the r ds(on) of the ideal diode mosfet to achieve the desired forward drop at maximum load. assum - ing a forward drop , ? v fwd of 30 mv across the mosfet: r ds(on) v fwd i load(max) = 30mv 7a = 4.2m the sir158dp offers a good choice with a maximum r ds(on) of 1.8 m at v gs = 10 v. the input capacitance c iss of the sir158dp is about 4980 pf. slightly exceeding the 10 recommendation, a 0.1 f capacitor is selected for c2 and c3 at the cpo pins. next, verify that the thermal ratings of the selected hot swap mosfet are not exceeded during power-up or an overcurrent fault. assuming the mosfet dissipates power due to inrush current charging the load capacitor c l at power-up, the energy dissipated in the mosfet is the same as the energy stored in the load capacitor, and is given by: e cl = 1 2 ? c l ? v in 2 for c l = 680 f, the time it takes to charge up c l is cal- culated as: t charge = c l ? v in i inrush = 680f ? 12v 1a = 8ms the inrush current is set to 1 a by adding capacitance c hg at the gate of the hot swap mosfet. c hg = c l ? i hgate(up) i inrush = 680f ? 10a 1a = 6.8nf choose a practical value of 10nf for c hg . the average power dissipated in the mosfet is calculated as: p avg = e cl t charge = 1 2 ? 680f ? 12v ( ) 2 8ms = 6w the mosfet selected must be able to tolerate 6 w for 8ms during power- up. the soa curves of the sir158dp provide 45w (1.5 a at 30 v) for 100 ms. this is sufficient to satisfy the requirement. the increase in junction temperature due to the power dissipated in the mosfet is ? t ?= ? p avg ?? ? zth jc where zth jc is the junction-to-case thermal impedance. under this condition, the sir158dp data sheet indicates that the junction temperature will increase by 3 c using zth jc = 0.5c/w (single pulse). next, the power dissipated in the mosfet during an overcurrent fault must be safely limited. the fault timer capacitor (c ft ) is used to prevent power dissipation in the mosfet from exceeding the soa rating during active current limit. a good way to determine a suitable value for c ft is to superimpose the foldback current limit profile shown in the typical performance characteristics on the mosfet data sheets soa curves. for the sir158dp mosfet, this exercise yields the plot in figure?6. 1ms 10ms 100ms 1s 10s dc bvdss limited i d limited i dm limited limited by r ds(on) * mosfet power dissipation curve resulting from foldback active current limit v ds ? drain-to-source voltage (v) i d ? drain current (a) 4235 f06 100 10 1 0.1 0.01 0.01 10 100 1 0.1 * v gs > minimum v gs at which r ds(on) is specified figure?6. sir158dp soa with design example mosfet power dissipation superimposed ltc 4235 4235f
18 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion as can be seen, the ltc4235 s foldback current limit profile roughly coincides with the 100 ms soa contour. since this soa plot is for an ambient temperature of 25 c only, a maximum fault timer period of much less than 100ms should be considered, such as 10 ms or less. selecting a 0.1f 10% value for c ft yields a maximum fault timer period of 1.75 ms which should be small enough to protect the mosfet during any overcurrent fault scenario. next, select the values for the resistive divider at the on pin that defines the undervoltage threshold of 9.7 v for the 12v supply at sense + . since the leakage current for the on pin can be as high as 1 a, the total resistance in the divider should be low enough to minimize the resulting offset error. calculate the bottom resistor r1 based on the following equation to obtain less than 0.2% error due to leakage current. r1 = v on(th) i in(leak) ? ? ? ? ? ? ? 0.2% = 1.235v 1a ? ? ? ? ? ? ? 0.2% = 2.4k choose r1 to be 2 k to achieve less than 0.2% error and calculating r2 yields: r2 = v in(uv) v on(th) C 1 ? ? ? ? ? ? ? r1 r2 = 9.7v 1.235v C 1 ? ? ? ? ? ? ? 2k = 13.7k the final components to consider are a 0.1 f bypass (c1) at the intv cc pin and a 0.1 f capacitor ( c4) connected between the reg and sense + pins. ? c4 d g d s d s d s s d s d s d g d s d s d s d g d ??? ? ? ? ? ? ? ?? ? ? ??? z2 z1 r s m h powerpak so-8 m d1 powerpak so-8 m d2 powerpak so-8 win1 via to in1 current flow to load c3 4235 f08 20 19 18 17 7 1 2 3 4 5 6 16 15 14 13 12 11 8 9 10 ltc4235ufd c2 r h c1 out w win2 current flow to load track width w: 0.03" per ampere on 1oz cu foil via to c2 (cpo1) via to dgate2 via to sense + via to gnd plane via to gnd plane via to gnd plane via to dgate1 via to c4 (reg) figure?7. recommended pcb layout for power mosfets and sense resistor ltc 4235 4235f
19 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion pcb layout considerations to achieve accurate current sensing, a kelvin connection for the sense resistor is recommended. the pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistor and the power mosfet should include good thermal management techniques for optimal device power dissipa - tion. a recommended pcb layout is illustrated in figure?7. connect the in and out pin traces as close as possible to the mosfets terminals. keep the traces to the mosfets wide and short to minimize resistive losses. the pcb traces associated with the power path through the mosfets should have low resistance. the suggested trace width for 1oz copper foil is 0.03 " for each ampere of dc current to keep pcb trace resistance, voltage drop and temperature rise to a minimum. note that the sheet resistance of 1oz copper foil is approximately 0.5 m/square, and voltage drops due to trace resistance add up quickly in high cur - rent applications. it is also important to place the bypass capacitor c1 for the intv cc pin, as close as possible between intv cc and gnd. also place c2 near the cpo1 and in1 pins, c3 near the cpo2 and in2 pins, and c4 near the reg and sense + pins. the transient voltage suppressors z1 and z2, when used, should be mounted close to the ltc4235 using short lead lengths. prioritizing supplies with d2off figure? 8 shows an application where the in1 supply is passed to the output on the basis of priority, rather than simply allowing the highest voltage to prevail. this is achieved by connecting a resistive divider from in1 at the d2off pin to suppress the turn-on of the ideal diode mosfet m d2 in the in2 power path. when the in1 supply voltage falls below 11.4 v, it allows the ideal diode mosfet m d2 , to turn on, causing the diode-or output to be switched from the main 12 v supply at in1 to the auxiliary 12 v supply at in2. this configuration permits the load to be supplied from a lower in1 supply as compared to in2 until in1 falls below the m d2 turn-on threshold. the threshold value used should not allow the in1 supply to be operated at more than one diode voltage below in2. otherwise, m d2 conducts through the mosfets body diode. the resistive divider connected from sense + at the on pin provides the undervoltage threshold of 9.7v for the diode-or output supply. backplane connector v main 12v v aux 12v card connector cpo1 gnd on fault pwrgd c l 470f 12v 5a r1 2k intv cc z2 smaj15a d2off in1 dgate1 dgate2 ltc4235 4235 f08 m d2 sir818dp m h sir818dp r s 0.004 hgate out sense + v sense + sense ? cpo2 c3 0.1f c4 0.1f in2 + r2 13.7k r6 100k r5 100k r h 10 r hg 1k c hg 10nf reg c2 0.1f c1 0.1f m d1 sir818dp en c ft 0.1f c5 0.1f z1 smaj15a ftmr imon adc r3 2.49k r4 21k c6 0.1f figure?8. plug-in card 12v prioritized power supply at in1 ltc 4235 4235f
20 for more information www.linear.com/ltc4235 a pplica t ions i n f or m a t ion backplane connector v main 12v v aux 12v card connector cpo1 gnd on fault pwrgd c l 470f 12v 5a r1 2k intv cc z2 smaj15a d2off in1 dgate1 dgate2 ltc4235 4235 f09 m d3 sir818dp m h sir818dp r s 0.004 hgate out sense + v sense + sense ? cpo2 c3 0.1f c4 0.1f in2 + r2 13.7k r6 100k r5 100k r h 10 r hg 1k c hg 10nf m d2 sir818dp reg c2 0.1f c1 0.1f m d1 sir818dp en c ft 0.1f c5 0.1f z1 smaj15a ftmr imon adc r3 2.49k r4 20k c6 0.1f r7 100 figure?9. 1v supply separation from in2 for prioritized power supply at in1 using back-to-back mosfets backplane connector v in1 12v v in2 12v card connector cpo1 gnd on fault pwrgd c l 220f 12v 10a r1 10k intv cc z2 smaj15a d2off in1 dgate1 dgate2 ltc4235 4235 f09 m d2 sir158dp m h sir158dp r s 0.002 hgate out sense + v sense + sense ? cpo2 c3 0.1f c4 0.1f in2 + r4 2.7k d2 d1 r3 2.7k r h 10 r hg 1k c hg 10nf reg c2 0.1f c1 0.1f m d1 sir158dp en pwren c ft 0.1f z1 smaj15a r snub1 100 c snub1 0.1f r snub2 100 c snub2 0.1f ftmr imon adc d1: green led ln1351c d2: red led ln1261cal figure?10. 12v, 10a card resident application ltc 4235 4235f
21 for more information www.linear.com/ltc4235 p ackage descrip t ion please refer to http://www .linear.com/product/ltc4235#packaging for the most recent package drawings. 4.00 0.10 (2 sides) 1.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or c = 0.35 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd20) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.65 0.05 2.50 ref 4.10 0.05 5.50 0.05 1.50 ref 3.10 0.05 4.50 0.05 package outline r = 0.05 typ 2.65 0.10 3.65 0.10 3.65 0.05 0.50 bsc ufd package 20-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1711 rev b) ltc 4235 4235f
22 for more information www.linear.com/ltc4235 ? linear technology corporation 2015 lt 1115 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc4235 r ela t e d p ar t s typical a pplica t ion part number description comments LTC4210 single channel hot swap controller operates from 2.7v to 16.5v, active current limiting, tsot23-6 ltc4211 single channel hot swap controller operates from 2.5 v to 16.5v , multifunction current control, msop-8, so-8 or msop-10 ltc4215 single channel hot swap controller operates from 2.9v to 15v, i 2 c compatible monitoring, ssop-16 or qfn-24 ltc4216 single channel hot swap controller operates from 0v to 6v, active current limiting, msop-10 or dfn-12 ltc4218 single channel hot swap controller operates from 2.9v to 26.5v, active current limiting, ssop-16 or dfn-16 ltc4221 dual channel hot swap controller operates from 1v to 13.5v, multifunction current control, ssop-16 ltc4222 dual channel hot swap controller operates from 2.9v to 29v, i 2 c compatible monitoring, ssop-36 or qfn-32 ltc4223 dual supply hot swap controller controls 12v and 3.3v, active current limiting, ssop-16 or dfn-16 ltc4224 dual channel hot swap controller operates from 1v to 6v, active current limiting, msop-10 or dfn-10 ltc4227 dual ideal diode and single hot swap controller operates from 2.9v to 18v, controls three n-channels, ssop-16 or qfn-20 ltc4228 dual ideal diode and hot swap controller operates from 2.9v to 18v, controls four n-channels, ssop-28 or qfn-28 ltc4229 ideal diode and hot swap controller operates from 2.9v to 18v , controls tw o n-channels, ssop-24 or qfn-24 ltc4352 low v oltage ideal diode controller operates from 0v to 18v, controls n-channel, msop-12 or dfn-12 ltc4353 dual low voltage ideal diode controller operates from 0v to 18v, controls tw o n-channels, msop-16 or dfn-16 ltc4355 positive high voltage ideal diode-or and monitor operates from 9v to 80v, controls tw o n-channels, so-16, dfn-14 or msop-16 ltc4357 positive high voltage ideal diode controller operates from 9v to 80v, controls n-channel, msop-8 or dfn-6 cpo1 gnd on fault pwrgd c l 1000f 12v 5a r1 2k intv cc bulk supply bypass capacitor d2off in1 dgate1 dgate2 ltc4235 4235 ta02 m d2 sir158dp m h sir158dp r s 0.004 hgate out sense + sense ? cpo2 c3 0.1f c4 0.1f in2 + r2 13.7k r h 10 r hg 1k c hg 10nf reg c2 0.1f c1 0.1f m d1 sir158dp en c ft 0.1f c5 0.1f bulk supply bypass capacitor ftmr imon adc backplane v in1 12v v in2 12v plug-in card 12v, 5a backplane resident ideal diode-or application with inrush current limiting ltc 4235 4235f

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